Free RISC-V Foundational Associate (RVFA) Practice Questions

Sample Practice Questions

Try these 10 sample questions from the RISC-V Foundational Associate (RVFA) practice bank. Each includes the answer and explanation. Continue with the interactive practice above to review the full question set.

1. 1Where did the RISC-V instruction set project begin?

   1. A.The Parallel Computing Laboratory at UC BerkeleyCorrect answer: A
   2. B.The Computer Laboratory at the University of Cambridge
   3. C.The Artificial Intelligence Laboratory at MIT
   4. D.The Department of Computer Science at Stanford

   Explanation: "Prof. Krste Asanović and graduate students Yunsup Lee and Andrew Waterman started the RISC-V instruction set in May 2010 as part of the Parallel Computing Laboratory (Par Lab) at UC Berkeley, of which Prof. David Patterson was Director." The project originated in Berkeley's Par Lab.

   Reference: About RISC-V International — History of RISC-V, Research at Berkeley

2. 2In RV32I, how many bits are in each integer x register?

   1. A.16 bits
   2. B.32 bitsCorrect answer: B
   3. C.64 bits
   4. D.128 bits

   Explanation: "For RV32I, the 32 x registers are each 32 bits wide, i.e., XLEN=32." The 32 registers each have XLEN of 32 bits.

   Reference: RV32I Base Integer Instruction Set, Version 2.1 — Programmers' Model for Base Integer ISA

3. 3Which CSR instruction uses a register mask to set writable bits in a CSR while returning its old value?

   1. A.CSRRSCorrect answer: A
   2. B.CSRRC
   3. C.CSRRW
   4. D.CSRRWI

   Explanation: "The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR." CSRRS returns the old value and sets the masked writable bits.

   Reference: Zicsr Extension for Control and Status Register Instructions — CSR Instructions

4. 4A developer wants GCC to compile RISC-V C source into an assembly file without assembling it. Which option should be used?

   1. A.-SCorrect answer: A
   2. B.-c
   3. C.-E
   4. D.-g

   Explanation: "-S ¶ Stop after the stage of compilation proper; do not assemble." The -S option outputs assembly without assembling.

   Reference: GCC Overall Options — Overall Options, -S

5. 5An S-mode trap handler inspects sstatus.SPP after a trap from U-mode. What does the field indicate?

   1. A.The previous privilege was user modeCorrect answer: A
   2. B.Supervisor interrupts were enabled before the trap
   3. C.The interrupt source is currently pending
   4. D.The exception PC contains the next instruction

   Explanation: "When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise." SPP identifies the previous privilege; SPIE stores prior supervisor interrupt enable.

   Reference: RISC-V Supervisor-Level ISA — 9.1.1. Supervisor Status Register

6. 6What does the V in the name RISC-V commemorate?

   1. A.Five standard privilege levels in the architecture
   2. B.A fifth generation following earlier Berkeley RISC projectsCorrect answer: B
   3. C.Five vendors that created the first processor design
   4. D.A vector extension included in every implementation

   Explanation: “The effort in 2010 to build a new RISC instruction set based on everything learned in the intervening 30 years was called RISC-V (“risk five”) to honor the prior Berkeley projects (RISC-I, RISC-II, …).” The name honors the earlier Berkeley RISC projects.

   Reference: RISC-V International FAQ — Why is it called RISC-V?

7. 7What value does an RV32I instruction read from register x0?

   1. A.The address of the current instruction
   2. B.The value last written to the register
   3. C.Zero in every bitCorrect answer: C
   4. D.The current stack pointer

   Explanation: "Register x0 is hardwired with all bits equal to 0." Writes do not make x0 hold a different value.

   Reference: RV32I Base Integer Instruction Set, Version 2.1 — Programmers' Model for Base Integer ISA

8. 8For CSRRS or CSRRC with rs1=x0, what happens to the addressed CSR?

   1. A.It is read without being writtenCorrect answer: A
   2. B.It is written with zero without being read
   3. C.It is read and then all its bits are cleared
   4. D.It is neither read nor written

   Explanation: "For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields." The CSR is read but no CSR write is attempted.

   Reference: Zicsr Extension for Control and Status Register Instructions — CSR Instructions

9. 9Which GCC option compiles or assembles a source file to an object file without linking?

   1. A.-E
   2. B.-S
   3. C.-cCorrect answer: C
   4. D.-o

   Explanation: "-c ¶ Compile or assemble the source files, but do not link." The -c option produces an object without linking.

   Reference: GCC Overall Options — Overall Options, -c

10. 10When a trap enters S-mode, what happens to the supervisor interrupt-enable state?

    1. A.SIE is copied to SPIE, and SIE is clearedCorrect answer: A
    2. B.SPIE is copied to SIE, and SPIE is cleared
    3. C.SIE is set and SPIE is cleared
    4. D.SIE and SPIE are both left unchanged

    Explanation: "When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0." The prior enable state is saved before supervisor interrupts are disabled.

    Reference: RISC-V Supervisor-Level ISA — 9.1.1. Supervisor Status Register